The present invention relates to memory circuits. More particularly, it relates to a memory circuit adapted for a semiconductor integrated circuit.
As a memory cell employing bipolar transistors, an arrangement as shown in FIG. 1 has been known. The memory cell in the figure is of the current switching type, and is made up of transistors Q.sub.1 and Q.sub.0 for readout, whose emitters are respectively connected to two data lines LD.sub.1 and LD.sub.0, transistors Q.sub.1 ' and Q.sub.0 ' for sustaining information, load resistances RC.sub.1 and RC.sub.0, a constant current circuit 5 which causes an information sustaining current IST to flow, and Schottky barrier diodes or conventional pn-junction diodes for speed-up D.sub.1 and D.sub.0 which are respectively connected between a word line X.sub.1 and the collectors of the transistors Q.sub.0 and Q.sub.1. The common connection point of the resistances RC.sub.1 and RC.sub.0 and the diodes D.sub.1 and D.sub.0 of the memory cell is connected through the word line X.sub.1 to a transistor QX.sub.1 for driving the word line, while the common connection point of the transistors Q.sub.1 ' and Q.sub. 0 ' is connected to the constant current circuit 5 for causing the sustaining current IST to flow. Connected to the respective data lines LD.sub.1 and LD.sub.0 are constant current source circuits 3 and 4 for causing a readout current IR to flow and driver circuits (transistors QS.sub.1, resistance R.sub.1) and (transistor QS.sub.0, resistance R.sub.0) receiving a voltage VREF.
In the above circuit, the information is sustained in such a way that either of the information sustaining transistor Q.sub.1 ' or Q.sub.0 ' is in the "on" state. The constant current circuit 5 supplies the sustaining current IST to the transistor Q.sub.1 ' or Q.sub.0 '. During an information sustaining period, the potential of the word line X.sub.1 is maintained at a low level by the transistor QX.sub.1, and the base potentials of the transistors Q.sub.1 and Q.sub.0 are lower than those of the transistors QS.sub.1 and QS.sub.0 of the driver circuits. As a result, the transistors Q.sub.1 and Q.sub.0 are in the "off" state.
In reading out the information, the potential of the word line X.sub.1 is made a high level in order that the base in the "on" state in the memory cell may become higher than the base potentials of the transistors QS.sub.1 and QS.sub.2 of the driver circuits and that the base potential of the transistor Q.sub.0 ' or Q.sub.1 ' in the "off" state may become lower than those of the transistors QS.sub.1 and QS.sub.0. As a result, either the transistor Q.sub.1 or Q.sub.0 of the memory cell attains the "on" state. The current IR of the constant current circuit 3 flows into the transistor QS.sub.1 or the transistor Q.sub.1 according to the stored content of the memory cell. Likewise, the current of the constant current circuit 4 flows into the transistor Q.sub.0 or QS.sub.0. As a result, a voltage according to the stored content of the memory cell appears across the collector resistance R.sub.1 or R.sub.0 of the transistor QS.sub.1 or QS.sub.0.
In writing the information, a potential difference is set between the base potentials of the transistors QS.sub.1 and QS.sub.0 according to the information to be written in. Owing to the potential difference, the current IR of the constant current circuit 3 or 4 flows into the transistor Q.sub.1 or Q.sub.0 to forcibly bring it into the "on" state.
The present memory cell is advantageous in that since the diodes D.sub.0 and D.sub.1 clamp the collector potentials of the transistors Q.sub.1 and Q.sub.0, the readout current IR can be made large, so the reading and writing at high speed are possible, and in that since the readout is executed through the emitters of the transistors of the memory cell, the sense can be constructed of a current switching type circuit, so the adaptability to an ECL (emitter coupled logic) circuit is good. Therefore, it is extensively used for memory cells of bipolar RAM's at present.
In most of the high-speed bipolar memories now in wide application, the degree of integration per chip is 1,024 bits or less. However, as the capacities of memory devices of computers have become large, the necessity for bipolar memories of or above 4,096 bits per chip has increased. In case where the prior-art memory cell shown in FIG. 1 is employed as the memory of or above 4,096 bits, a problem as stated below arises. In case of raising the degree of integration per chip of a semiconductor integrated circuit (IC), it is common practice that the degree of integration is raised with the power dissipation per chip left intact (usually, e.g. about 500 mW/chip). The reason is that the allowable power dissipation per chip is limited because an IC package for receiving one chip is ordinarily a package having 14 to 18 dual in-line pins.
In rendering the degree of integration high, accordingly, the power dissipation as a whole is usually made substantially the same value as the previous value. Therefore, the power dissipation per bit of the memory circuit must be lowered. When the memory cell in FIG. 1 is employed for a memory of 1 Kbits (1,024 bits)/chip, the sustaining current IST is made a value of e.g. 25 .mu.A-50 .mu.A/ bit, resulting in a value of approximately 25mA-50 mA for all the 1,024 bits. When a memory of 4,096 bits/chip is to be realized while keeping this value unchanged, the sustaining current per bit needs to be 6 .mu.A-12.mu.A or less. In case of reducing the sustaining current in this manner, in order to endow the transistors Q.sub.1 ' and Q.sub.0 ' of the memory cell with appropriate sustaining operation potentials, it is required to make the resistance value of the collector resistors RC.sub.1 and RC.sub.0 a high resistance value, for example, a value of about 100K.OMEGA..
However, in the case of intending to put the foregoing circuit into the high degree of integration by diminishing the sustaining current as described above, the readout of information becomes difficult as explained hereunder.
It is supposed by way of example that the transistor Q.sub.0 ' of the memory cell is in the "on" state, while the transistor Q.sub.1 ' is in the "off" state, and that the information is read out through the transistor Q.sub.0. Assuming the readout current IR to be 0.5 mA and the current gain h.sub.FE of the transistor Q.sub.0 to be 50 at this time, the base current of the transistor Q.sub.0 becomes 10 .mu.A (=0.5 mA/50). This base current causes a voltage drop across the 100K.OMEGA." collector resistor RC.sub.1, resulting in lowering the base potential of the transistor Q.sub.0. In the absence of the diode D.sub.1, a voltage drop which is as great as 1V will arise across the resistor RC.sub.1. Owing to the presence of the diode D.sub.1, however, the voltage drop of 0.8 V which agrees with the forward voltage thereof takes place. Accordingly, the potential of a nodal point VC.sub.1 becomes: EQU VC.sub.1 =VX.sub.1 -0.8 (V)
On the other hand, the collector potential VC.sub.0 of the transistor Q.sub.0 turned "on" is clamped by the diode D.sub.0 and therefore becomes: EQU VC.sub.0 =VX.sub.1 -0.8 (V)
so that VC.sub.1 =VC.sub.0. That is, assuming that the transistor Q.sub.0 is turned "on", the transistor Q.sub.1 is also turned "on". It is consequently impossible to design the memory cell so that the readout current IR may fully flow from the transistor Q.sub.0 without destroying the content of the memory cell. In case of the 1 Kbit memory, the resistance of the resistor RC.sub.1 is about 15K.OMEGA., and hence: EQU VC.sub.1 =VX.sub.1 -0.15 (V) EQU VC.sub.0 =VX.sub.1 -0.8 (V)
Since VC.sub.1 &gt;VC.sub.0, the normal readout is possible.
As understood from the foregoing, although the prior art memory cell illustrated in FIG. 1 is advantageous in that the readout currents can be made great owing to the function of the clamp diodes D.sub.0 and D.sub.1, it gives rise to the disadvantage that the large readout currents are impossible when a memory cell of large bit capacity is designed by suppressing the sustaining currents to below a certain degree.